ASML's High-NA queue stretches into 2028 as U.S. logic fabs bid for scarce tools
The lithography bottleneck is no longer a rumor. It is a delivery calendar.
Semiconductor cleanroom equipment
SAN JOSE, Calif. — Chipmakers racing toward 2-nanometer-class logic are discovering that the scarce asset is not a design library or a GPU allocation. It is calendar time on ASML's High-NA EUV tools, and the queue now stretches into 2028 for several U.S. customers.
Two supplier executives said installation crews, not factory floors, have become the binding constraint. Each High-NA scanner requires a specialized team that can spend months aligning optics after the crate lands. That labor pool does not grow as fast as capital budgets in Arizona, Texas, and New York.
The commercial implication is blunt. Foundries that miss a slot do not merely delay a process node; they delay the entire AI accelerator tape-out that their hyperscale customers have already booked as 2027 revenue. Procurement teams are treating lithography reservations the way airlines treat takeoff slots: hoard them, trade them, and never let them go unused.
James Whitaker
Technology Editor
Reports on semiconductors, cloud infrastructure, and the industrial politics of AI.